The present disclosure relates to semiconductor devices and methods for fabricating the same, and more particularly relates to a semiconductor device having a three-dimensional structure and including a fin-shaped semiconductor region on a substrate.
In recent years, with increases in the degree of integration, functionality, and speed of semiconductor devices, there is an increasing demand for miniaturization of semiconductor devices. To meet the demand, various device structures have been proposed for reducing the area occupied by transistors over a substrate. Among them, a field effect transistor having a tin-type structure has drawn attention. The field effect transistor having the fin-type structure is generally called a fin field effect transistor (fin-FET), and has an active region made of a semiconductor region (hereinafter referred to as a fin-type semiconductor region) having a thin-wall (fin) shape perpendicular to the principal surface of a substrate. In the fin-FET, the side surfaces of the fin-type semiconductor region can be used as channel surfaces, and accordingly the area occupied by transistors over the substrate can be reduced (see, e.g., Japanese Patent Publication No. 2006-196821 and D. Lenoble et al., “Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions,” 2006 Symposium on VLSI Technology Digest of Technical Papers, p. 212).
In Japanese Patent Publication No. 2006-196821, a technique has been proposed in which ions are implanted into a fin-type silicon region from oblique directions, thereby forming extension regions and high-concentration impurity regions which serve as source/drain regions. When, e.g., an impurity region is formed by such ion implantation from oblique directions, ions are implanted into side portions of the fin-type silicon region from one direction while ions are implanted into an upper portion of the fin-type silicon region from two directions. This allows the implant dose of an impurity region in the upper portion of the fin-type silicon region to be twice as large as the implant dose of an impurity region in each of the side portions of the fin-type silicon region. In other words, it is difficult to form a low-resistance impurity region in the side portion of the fin-type silicon region.
Therefore, in recent years, attention has been drawn to the use of plasma doping in order to dope the side surfaces of a fin-type semiconductor region with impurities.
A pulsed DC plasma technique has been proposed, as a plasma doping technique for forming an impurity region of a fin-FET, in D. Lenoble et al., “Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions,” 2006 Symposium on VLSI Technology Digest of Technical Papers, p. 212. In the pulsed DC plasma technique, a plasma is generated intermittently, and thus, this technique has an advantage in that etching of a fin-type semiconductor region can be reduced.
A plasma doping technique using an inductively coupled plasma (ICP) method has been proposed, as a plasma doping technique for forming an impurity region of a fin-FET, in WO 2006/064772. The ICP method has an advantage in that the surface of a large substrate, such as a wafer having a diameter of 300 mm, can be uniformly doped by employing a longer time range (doping time) than that used in a pulsed DC plasma method.
Japanese Patent Publication No. H01-295416 describes a plasma doping technique for doping the trench side surface, although it is not an object of the technique to subject the side surfaces of a narrow and fine fin-type semiconductor region to plasma doping.